Microprocessor without Interlocked Pipelined Stages (MIPS) Architecture
- is a family of reduced instruction set compute (RISC) instruction set architectures (ISA)
- developed by MIPS Computer Systems, now MIPS Technologies, based in the United States
- is a load/store architecture (also known as a register-register architecture); except for the load/store instructions used to access memory
- all instructions operate on the registers
Subpages
MIPS - Versions
- MIPS I, II, III, IV, and V
- MicroMIPS
MIPS - Instruction Formats
|
3 Instruction Types |
-31- format (bits) -0- | |||||
|---|---|---|---|---|---|---|
|
Register (R) |
opcode (6) |
rs (5) |
rt (5) |
rd (5) |
shamt (5) |
funct (6) |
|
Instruction (I) |
opcode (6) |
rs (5) |
rt (5) |
immediate (16) | ||
|
Jump (J) |
opcode (6) |
address (26) | ||||
MIPS - Pipeline
MIPS has 5 stages in pipeline instruction execution
- fetch - pull the instruction from RAM into the processor
- decode - determine the type of the instruction and extract the operands (e.g., the register indices, the immediate value, etc)
- execute - if necessary, perform the arithmetic operation that is associated with the instruction
- memory - if necessary, read or write a value from/to RAM
- writeback - if necessary, update a register with the result of an arithmetic operation or a RAM read