RISC-V

RISC-V Landscape

See: https://landscape.riscv.org

RISC-V Bases

• RV32I - Base Integer Instruction Set, 32-bit
• RV32E - Base Integer Instruction Set (embedded), 32-bit, 16 registers with a smaller instruction set
• RV64I - Base Integer Instruction Set, 64-bit
• RV128 - Base Integer InstructionSet, 128-bit

RISC-V Extensions

Once we have the base we can add extensions to it to define the exact features of the core:

• M – Standard Extension for Integer Multiplication and Division
  • RV32M extension implements 8 instructions
  • RV64M adds 5 instructions to those 8
• A – Standard Extension for Atomic Memory Instructions
• F – Standard Extension for Single-Precision Floating-Point
• D – Standard Extension for Double-Precision Floating-Point
  • double-precision floating-point registers f0 to f31 are now 64-bit wide
• G – Shorthand for the base and above extensions
• Q – Standard Extension for Quad-Precision Floating-Point, introducing 128-bit wide floating point registers
• L – Standard Extension for Decimal Floating-Point operations
• C – Standard Extension for Compressed Instructions
• B – Standard Extension for Bit Manipulation
• J – Standard Extension for Dynamically Translated Languages such as C#, Go, Haskell, Java, JavaScript, OCaml, PHP, Python, R, Ruby, Scala or WebAssembly
• T – Standard Extension for Transactional Memory
• P – Standard Extension for Packed-SIMD Instructions
• V – Standard Extension for Vector Operations
• N – Standard Extension for User-Level Interrupts
• H – Standard Extension for Hypervisor
• S – extension, for supervisor operation
• H – extension, for hypervisor operation
• Zicsr extension, for manipulating CSR registers
• Zifencei extension, for instruction memory synchronization

RISC-V Registers

Subpages

• RISC-V Processors
• RISC-V Pseudoinstructions

Resources

• https://riscv.org/
• RISC-V Card.pdf