High Bandwidth Memory (HBM) HBM2/HBM3
- is a computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM)
- initially from Samsung, AMD and SK Hynix
HBM - Versions
|
Generation |
Release Year |
Pin Speed (Data Rate) |
Clock Freq. (Typ.) |
Bus Width (Interface) |
Stack Height (Max) |
Max Capacity (Per Stack) |
Bandwidth (Per Stack) |
|
HBM1 |
2013 |
1.0 Gbps |
500 MHz |
1024-bit |
4-Hi |
4 GB |
128 GB/s |
|
HBM2 |
2016 |
2.0 Gbps |
1.0 GHz |
1024-bit |
8-Hi |
8 GB |
256 GB/s |
|
HBM2E |
2019 |
3.2–3.6 Gbps |
1.6–1.8 GHz |
1024-bit |
12-Hi |
16–24 GB |
410–460 GB/s |
|
HBM3 |
2022 |
6.4 Gbps |
3.2 GHz |
1024-bit |
16-Hi |
24–32 GB |
819 GB/s |
|
HBM3E |
2023 |
9.2–9.8 Gbps |
4.6–4.9 GHz |
1024-bit |
12-Hi / 16-Hi |
36–48 GB |
1.2 TB/s |
|
HBM4 |
2025* |
11.7–13 Gbps |
5.8–6.5 GHz |
2048-bit |
12-Hi / 16-Hi |
48–64 GB |
2.8–3.3 TB/s |
Use Cases
- can be used as VRAM