Tutorials based on: https://www.chipverify.com/verilog/verilog-assign-statement
- Verilog - 1 - Data Types
- Verilog - 2 - Module
- Verilog - 3 - Ports
- Verilog - 4 - Module Instantions
- Verilog - 5 - Assign／Assigment Statements
- Verilog - 6 - Operators
- Verilog - 7 - always Block
- Verilog - 8 - intial Block
- Verilog - 9 - generate Block
- Verilog - 10 - Behavorial Modeling
- Verilog - 11 - Gate／Switch Modeling
- Verilog - 12 - Simulation
- Verilog - 13 - System Tasks and Functions
- Verilog - 14 - Code Examples