Opens this exact state, paused.
Details
Sources
- MIT Computation Structures — Memory hierarchy (6T SRAM, 1T1C DRAM, sense/restore, refresh)
- Cornell CS3410 — Caches
- KIOXIA — What is NAND flash? (low Vt = 1, high Vt = 0, series cells)
- KIOXIA — Multi-level cell (Vt distributions, multi-bit)
- KIOXIA — Technical glossary (NOR parallel, floating gate, SSD controller)
- KIOXIA — Charge-trap layer in 3D flash (more word-line layers for density, taller stacks, charge-trap layer)
- Micron — NOR flash (serial/parallel interfaces)
- Micron — 2550 SSD (DRAM-less via HMB)
- NVIDIA — Turing in depth (L0 instruction cache, L1/shared, GDDR6)
- NVIDIA — Ampere in depth (A100 L1/shared, L2, HBM2)
- Micron — HBM (stacked DRAM dies, optional base die, TSVs + microbumps, wide interface)
- AMD — 3D V-Cache technology (extra SRAM cache die stacked on the compute die)