RISC-V Pseudoinstructions

RISC-V Pseudoinstructions

Pseudoinstruction

Implementation

Meaning

nop

addi x0, x0, 0

No operation

beqz rs, offset

beq rs, x0, offset

Branch if equal to zero

j offset

jal x0, offset

Unconditional jump

jal offset

jal x1, offset

Jump and link

jr rs

jalr x0, 0(rs)

Jump register

ret

jalr x0, 0(x1)

Return from subroutine

lla rd, symbol

auipc rd, symbol[31:12]
addi rd, rd, symbol[11:0]

Load local address

li rd, immediate

lui rd, immediate[31:12]
addi rd, rd, immediate[11:0]

Load Immediate

mv rd, rs

addi rd, rs, 0

Copy register

not rd, rs

xori rd, rs, -1

One’s complement

bgt rs, rt, offset

blt rt, rs, offset

Branch if greater than

call offset

auipc x1, offset[31:12]
jalr x1, offset11:0

Call far-away subroutine